MAC7200 datasheet(471/976 Pages) FREESCALE

471 / 976 page

Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

393

In all late write hit cases, no additional wait states are inserted on the AHB. For each case in which a read

is requested, if the data all of the data is not in the late write buffer, the missing data is requested and the

read data mux (shown in Figure 19-2 before the decode block) will select the between the late write buffer

and pram_rdata.

The timing diagram in Figure 19-8 shows two cases. The first read request demonstrates the case when

all read data required is present in the late write buffer. The second case, a read modify write demonstrates

the case when only part of the data is in the late write buffer.

Figure 19-8. Late Write Hits

1. Late Write Buffer

2. 64-bit address A

3. address bit A[2]=0

4. address bit A[2]=1

5. address bit A[2]=either 1 or 0

6. any valid value can be substituted

345

addr y

nonseq

idle

word

long

data y

addr y+4

addr y

2'b11

2'b10

2'b11

2'b00

data y+4

64-bit data y

32-bit upper data y

64-bit data y

hclk

haddr

htrans

hwrite

hunalign

hsize

hready

hwdata

hrdata

pram_addr

pram_we

pram_cs_b

pram_rdata

pram_wdata

late write buffer

rmw reg

Note: rmw reg : read/modify/write register shown in Figure 19-2.

MAC7200 Datasheet(PDF) 471 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 471 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL