MAC7200 datasheet(468/976 Pages) FREESCALE

468 / 976 page

Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

390

Freescale Semiconductor

Figure 19-6. Back to Back 32/64-bit Writes

19.2.3.5.2

Less than 32-bit Writes

Less than 32-bit writes require a three step process referred to as a read/modify/write operation. Each

32-bit location must be initialized with a valid codeword created by the ECC encode block shown in

Figure 19-2. This codeword must be kept consistent with the entire 32-bit word. Therefore, for each less

than 32-bit write, the array data must be read (read), the AHB write data merged with the array data and

the codeword regenerated (modify), before the data can be stored (write).

As shown in Figure 19-2, the array read data is registered after it is decoded and before it is merged with

the AHB write data. Therefore, every less than 32-bit write requires that one wait state be inserted before

the data phase can be completed. This is shown in Figure 19-8. In cycle 3, the AHB data phase completes

and the write data is registered in the late write buffer. It is stored to memory on the next available array

access. The next available array access is during cycle 4 while the read for ’addr z’ is being decoded.

addr y

addr y+32

addr z

nonseq

idle

word

long

data y

data y+32

addr y

addr z

addr y+32

2'b10

2'b00

2'b01

2'b11

data z

data y

data y+32

hclk

haddr

htrans

hwrite

hsize

hready

hrdata

hwdata

pram_addr

pram_we

pram_cs_b

pram_rdata

pram_wdata

late write buffer

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