MAC7200 datasheet(465/976 Pages) FREESCALE

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Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

387

Single-bit corrections cause the output ecc_single_error to be asserted. Multiple-bit errors cause the

ecc_multi_error output to be asserted as well as an AHB ERROR response to be generated (see AMBA

AHB spec 2.0, pg 3-23). AHB address attributes are also saved and outputted for each case. These two

flags are mutually exclusive.

The assertion of these two flags may cause an interrupt to be generated, the EER bit to be set in the

Miscellaneous Control Module (MCM), and the errored address, syndrome, parity and master address to

be saved in the MCM (See Chapter 13, “Miscellaneous Control Module (MCM) for a programming

model). Conclusive research has not been done to investigate the effect of more than 2 errors, although

the third and fourth entry of Table 19-6 have been put in place to catch some of these.

Finally, note that for the 64-bit implementation, if the read access size is less than 64 bits, only ECC errors

within the 39-bit code word that is applicable to the read can cause a bus error. However, all ECC errors

will still be reported.

19.2.3.2

Max Address

The input pram_max_addr[17:0] is static and reflects the maximum 32-bit data address (eg.

pram_max_addr[17:0] is the equivalent notation of haddr[19:2]) available for use in the attached memory.

This funtionality allows for non power of 2 memory arrays to be used. AHB requests to addresses above

this value will be terminated with an ERROR response. This input should be used with the input

pram_size[3:0] in the following way.

To indicate the memory array size, pram_max_addr[17:0] should be set to the maximum addressable row.

pram_size[3:0] should be set to a value above what the value of pram_max_addr[17:0] indicates. For

example, to indicate a 48KB memory (12,288 32-bit addresses):

•

pram_size[3:0] = 4’b1000 or 64KB.

•

pram_max_addr[17:0] = 18’h 02fff (greates 32-bit address without crossing 48KB boundary)

•

Then, if haddr[19:0] >= 20’h 0c000, an ERROR response will be generated.

19.2.3.3

Read / Write Introduction

As stated earlier in the ECC Overview, it is essential that each memory address be written to a known value

before it is read. This includes reads generated from the read / modify / write operation which occurs when

a write transfer of less than 32 bits is requested (see Section 19.2.3.5.2, “Less than 32-bit Writes”).

The basic protocol of the AMBA AHB dictates that each address phase is acknowledged with hready and

is followed by the corresponding data phase. PRAM read transfers work in the same manner but lack a

transfer acknowledge. It is assumed that all PRAM phases execute in a single cycle. PRAM write data

phases, however, are issued and complete at the same time as the address phase. This behavior is

demonstrated in Figure 19-7 in cycles 4 and 5.

In the following timing diagrams, pram_cs_b is always represented in the 64-bit implemenation as a 2-bit

field. Since the 32-bit implementation is a subset of the 64-bit implementation, one should be able to infer

the behavior of the chip select signal and the controller if there were only one chip select available and the

AHB bus was only 32 bits wide. Most of the diagrams depicting 64-bit transfers are shown for specific

cases for the 64-bit implementation.

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