MAC7200 datasheet(462/976 Pages) FREESCALE

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Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

384

Freescale Semiconductor

mcm_errbit

This vector defines the bit position which is logically complemented to create the specific data inversion

on a write operation. It is defined as:

00 pram_wdata[0] of the odd bank is inverted

01 pram_wdata[1] of the odd bank is inverted

...

31 pram_wdata[31] of the odd bank is inverted

32 pram_wdata[0] of the even bank is inverted

33 pram_wdata[1] of the even bank is inverted

...

63 pram_wdata[31] of the even bank is inverted

64 pram_wdata_ecc[0] of the odd bank is inverted

65 pram_wdata_ecc[1] of the odd bank is inverted

66 pram_wdata_ecc[2] of the odd bank is inverted

67 pram_wdata_ecc[3] of the odd bank is inverted

68 pram_wdata_ecc[4] of the odd bank is inverted

69 pram_wdata_ecc[5] of the odd bank is inverted

70 pram_wdata_ecc[6] of the odd bank is inverted

71 pram_wdata_ecc[0] of the even bank is inverted

72 pram_wdata_ecc[1] of the even bank is inverted

73 pram_wdata_ecc[2] of the even bank is inverted

74 pram_wdata_ecc[3] of the even bank is inverted

75 pram_wdata_ecc[4] of the even bank is inverted

76 pram_wdata_ecc[5] of the even bank is inverted

77 pram_wdata_ecc[6] of the even bank is inverted

All mcm_errbit unused values are reserved and unused. For the 32bit operation, values of mcm_errbit

from 32-64 and 71-77 are also reserved and unused.

hresp

The two msb of this field are tied to 0 allowing for the following supported encodings:

000 OKAY

001 ERROR which is asserted for the required two cycle response to signal an ecc_multiple_error

assertion or violation of the pram_max_addr field.

nnn All other encodings are reserved and never generated by the PRAM controller.

pram_cs_b

This is the active-low chip select. For the 64 bit implementation, there are 2 chip selects, each of which

controls a 39 bit wide memory. The chip selects for this implementation are described in Table 19-5. For

each chip select:

0 an active, qualified memory array cycle

1 an idle memory array cycle

Table 19-4. Signal Property Details (Continued)

Name

Description

Table 19-5. pram_cs_b 64 Bit Behavior

Acess Type haddr[2] pram_cs_b[1] pram_cs_b[0]

Description

IDLE

—

No access

≤ 32 bit

Even bank accessed

≥ 32 bit

Odd bank accessed

> 32 bit

—

Both banks accessed

MAC7200 Datasheet(PDF) 462 Page - Freescale Semiconductor, Inc

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