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MAC7200 Datasheet(PDF) 461 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 461 Page - Freescale Semiconductor, Inc |
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461 / 976 page ![]() Platform RAM Array Controller (PRAM_CTL) MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 383 differences in functionality between the 2.v6 spec and the PRAM implementation. Signals which are exclusive to this block and not sufficiently described in Table 19-3 are further defined as well. See Section 19.2.3.2, “Max Address,” for a more detailed description. Table 19-4. Signal Property Details Name Description htrans A state of BUSY is not supported and furthermore is regarded as IDLE 01 IDLE - no transfer required 01 BUSY - not supported 01 NSEQ - first transfer of burst or single transfer 11 SEQL - burst transfer pram_size Supported power of 2 RAM array sizes are: 0111 32KB 1000 64KB 1001 128KB 1010 256KB 1011 512KB 1100 1024KB pram_max_addr This input defines the maximum address of the attached memory array. This functionality allows non-power-of-2 memories to be supported. See Section 19.2.3.2, “Max Address,” for a more detailed description. mcm_con_1bi When asserted, one bit of write data is inverted continously on each active pram write cycle. This inserts a single correctable error is inserted at these locations. mcm_one_1bi When asserted, one bit of write data is inverted, one time only, on the next active pram write cycle. This inserts a single correctable error at this location. mcm_con_nci When asserted, one bit of write data is inverted continously on each active pram write cycle. In addition, the overall parity bit associated with the active bank (pram_wdata_ecc[0]) is inverted. This inserts a multiple bit non correctable error at these locations. mcm_one_nci When asserted, one bit of write data is inverted continously on each active pram write cycle. In addition, the overall parity bit associated with the active bank (pram_wdata_ecc[0]) is inverted. This inserts a multiple bit non correctable error at this location. |
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