MAC7200 datasheet(463/976 Pages) FREESCALE

463 / 976 page

Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

385

The memory map for the PRAM memory space is determined by the system in which the controller is

implemented. There are no program-visible registers within the controller. All ECC error reporting and

forcing capabilities are implemented via program-visible registers located in the Miscellaneos Control

Module (MCM).

19.2.3

Functional Description

19.2.3.1

Error Correcting Code (ECC)

19.2.3.1.1

Overview

The PRAM_CTL memory controller uses a 7-bit error correcting code (ECC) to correct single-bit errors

and detect multiple-bit errors within the 32-bit data field. For the 64-bit implementation, the 32-bit encode

and decode is effectively duplicated to work on 64 bits for a total of 14 bits of ECC. Since the ECC bits

are written to and read from memory with the data, it is essential that each 32-bit memory location be

written to a known value before being read. If an uninitialized memory address is read, it is likely the read

will result in a multiple-bit ECC error and an errored transaction on the AHB. Only 32-bit and 64-bit write

transfers can be used to initialize the memory as 16-bit or 8-bit writes will generate a read/modify/write

scenario (see Section 19.2.3.5.2, “Less than 32-bit Writes”). As shown highlighted in blue in Figure 19-2,

the ECC is composed of two modules, the encoder and the decoder. The decode module is shown in

greater detail in Figure 19-3 below.

pram_we

This is the read or write flag.

0 read operation

1 write operation

ecc_single_error Flag to indicate a single error correction has occurred. This signal is only valid when hready is asserted.

ecc_multi_error

Flag to indicate a multiple-bit, non-correctable error has occurred. This signal starts the ERROR

response on the AHB. ecc_syndrome, ecc_address, and ecc_hmaster information is valid when this flag

and hready are asserted. A multiple-bit error is defined as a non-zero syndrome and odd ecc_parity, or

even ecc_parity and an out of range syndrome.

ecc_syndrome

There is a 6bit syndrome field generated for each 32 bits of data width. The syndrome can be used to

determine the bit position of the errored bit within each of the 39 bits of data read from the array. See the

table of ECC bits vs. data bits to determine which syndrome relates to which data bit.

ecc_parity

This is the overall parity of the data decoded, based on an odd parity scheme.

ecc_<attribute>

This refers to the final four entries in Table 19-2. These signals reflect the state of the AHB signals with

corresponding attribute name in the address phase of the AHB transfer. For example, ecc_hprot reflects

the AHB HPROT state when this transfer was requested.

Table 19-4. Signal Property Details (Continued)

Name

Description

MAC7200 Datasheet(PDF) 463 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 463 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL