MAC7200 datasheet(460/976 Pages) FREESCALE

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Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

382

Freescale Semiconductor

19.2.2.2

Detailed Signal Descriptions

Signals beginning with "h" correspond to the AMBA AHB bus. Their description can be found in the

AMBA AHB-Lite 2.v6 specification. The signal descriptions below are provided to describe the

pram_rdata

input

read data from array to controller

d.width

pram_rdata_ecc

input

ecc bits for read data from array

ecc.width

pram_size

input

static size of RAM array

0ns (static)

pram_max_addr

input

maximum addressable memory space

0ns (static)

mcm_con_1bi

input

force continuous single bit correctable errors

Clk_Period

× 0.2

mcm_one_1bi

input

force one single bit correctable error

Clk_Period

× 0.2

mcm_con_nci

input

force continous multiple bit non-correctable errors

Clk_Period

× 0.2

mcm_one_nci

input

force one multiple bit non-correctable error

Clk_Period

× 0.2

mcm_errbit

input

bit position to inject error

Clk_Period

× 0.2

hclk

input

platform system clock

N/A

hresp

output

AHB transfer response

Clk_Period

× (1 - 0.3)

hready

output

AHB acknowledge

Clk_Period

× (1 - 0.3)

hrdata

output

AHB read data bus

d.width

Clk_Period

× (1 - 0.3)

pram_addr

output

array address

a.width

pram_wdata

output

write data to array

d.width

pram_wdata_ecc

output

write data ecc bits to array

ecc.width

pram_cs_b

output

chip select active low

cs.width

pram_we

output

write enable, high equals write

ecc_single_error

output

single error found flag

cs.width

Clk_Period

× (1 - 0.6)

ecc_multi_error

output

multiple errors found flag

cs.width

Clk_Period

× (1 - 0.6)

ecc_syndrome

output

bit position of error

cs.width

Clk_Period

× (1 - 0.6)

ecc_parity

output

overall parity of data decoded

ecc.width -

cs.width

Clk_Period

× (1 - 0.6)

ecc_haddr

output

address of error

Clk_Period

× (1 - 0.6)

ecc_hmaster

output

master initiating errored transfer

Clk_Period

× (1 - 0.6)

ecc_hsize

output

size of errored transfer

Clk_Period

× (1 - 0.6)

ecc_hprot

output

protection of errored transfer

Clk_Period

× (1 - 0.6)

ecc_hwrite

output

direction of errored transfer

Clk_Period

× (1 - 0.6)

1. See Appendix A, “Electrical Characteristics” for signal timing constraints.

Table 19-3. Signal Properties (Continued)

Name

Port

Function

Width

Timing

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