MAC7200 datasheet(459/976 Pages) FREESCALE

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Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

381

19.2.2

PRAM_CTL Interface Description

19.2.2.1

Overview

Table 19-3 lists all block inputs and outputs. Each signal has a corresponding bit width (Width) and

timing constraint (Timing). Input timing constraints are defined as the percentage of the clock cycle, or

delay in nanoseconds, before the input is valid. Output timing constraints are defined as the percentage of

the clock cycle, or delay in nanoseconds, after the output is valid. These delays are specified in the form:

Eqn. 19-1

Eqn. 19-2

where Clk_Period refers to the period in nanoseconds, Relative_Input_Delay refers to the amount of

time before the input is valid at the interface, and Relative_Output_Delay refers to the amount of time

before the output is valid at the interface. Note that timing associated with pram* signals are not related

to the system clock and therefore static.

Table 19-2 lists the width variables used in Table 19-3 and their corresponding values depending on the

data width implementation.

Table 19-2. Signal Width Variables

Name

32 bit

64 bit

d.width

a.width

ecc.width

cs.width

Table 19-3. Signal Properties

Name

Port

Function

Width

Timing

hreset_b

input

asynchronous platform reset, active-low

See Note 1

hsel_pram

input

select for pram slave

Clk_Period

× 0.60

htrans

input

AHB type of transaction

Clk_Period

× 0.60

haddr

input

AHB address bus

Clk_Period

× 0.60

hwdata

input

AHB write data

d.width

Clk_Period

× 0.45

hsize

input

AHB size of transfer

Clk_Period

× 0.60

hbstrb

input

AHB byte strobes

d.width / 8

Clk_Period

× 0.60

hwdata

input

AHB write data

d.width

Clk_Period

× 0.60

hburst

input

AHB burst transaction type

Clk_Period

× 0.60

hmaster

input

AHB master address

Clk_Period

× 0.60

hunalign

input

AHB unalign transfer flag

Clk_Period

× 0.60

Input Constraint

Clk_Period

Relative_Input_Delay

Output Constraint

Clk_Period

Relative_Output_Delay

–

()

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