MAC7200 datasheet(455/976 Pages) FREESCALE

455 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

377

Chapter 19 SRAM and SRAM Controller

19.1

SRAM

19.1.1

SRAM Features

•

Single port RAM with chip enable/select and 1 byte write enable per byte, used for system RAM

•

Memory Map: 20KByte block on a 32KByte boundary (MAC72x2) or 32kByte block(MAC72x1),

byte addressable

•

Start Address determined by 3-bit base address of slave port in the crossbar switch. Within the

512Mb space for each crossbar switch slave port, the SRAM is replicated n times, to fill the entire

space. This allows the user to access the SRAM anywhere in the 512Mb space on a 32Kb boundary.

•

Built in ECC (2-bit detection)

19.1.2

SRAM Protocol

There is no protocol associated with the SRAM controller other than the standard AHB-Lite v2.0.

19.1.3

SRAM External Pins

There are no SRAM signals that drive or are driven from MCU pins.

19.1.4

SRAM Bus Aborts

There are two situations in which access to the SRAM can be aborted:

•

On the MAC72x2, the access results in an ECC Error. Please refer to Section 19.2.3.1, “Error

Correcting Code (ECC) for more details on handling this type of abort.

•

The access is between SRAM_BASE_ADDRESS + $5000 and SRAM_BASE_ADDRESS +

$7FFF. i.e.-between the 20K and 32K address range of the SRAM. Note that above 32K, the

address range is mirrored (Please see Section 19.1.6.2, “SRAM Address Mirroring).

19.1.5

SRAM Differences from MAC71xx

•

On the MAC72x2, changed memory size from 32K to 20K. Memory map wrap-around is 32K, not

20K.

•

Added ECC capability. See Chapter 13, “Miscellaneous Control Module (MCM) for more details

on the ECC reporting on the MAC72x2.

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