MAC7200 datasheet(466/976 Pages) FREESCALE

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Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

388

Freescale Semiconductor

19.2.3.4

Reads

Figure 19-2 shows the read data path through the PRAM_CTL. All read transfers, of any size, complete

with a zero wait states response on the AHB. Figure 19-4 shows a few examples of the timing of read

transfers on the controller’s interfaces. Whether the type of the transfer is sequential or nonsequential,

there is no difference in the timing of the controller. Furthermore, reads of less than 32 bits in size are

treated exactly the same as a 32-bit read. For the 64-bit implementation, in order to save power, only the

applicable chip select is asserted for transfers of 32 bits or less (see Table 19-5).

Figure 19-4. 64-bit Read Followed by Two 32-bit Reads

19.2.3.4.1

Unaligned Reads

Any unaligned read will execute as if the size of the transfer, as defined by the hsize, is equal to the

corresponding unaligned container size. For example, a 32-bit unaligned read will have a container of 64

bits and therefore the controller will execute the read as if it were a 64-bit read. See Table 4-5 for more

information on unaligned accesses.

19.2.3.5

Writes

19.2.3.5.1

32-bit / 64-bit Writes

The write data path is shown in Figure 19-2, highlighted in blue. Aligned 32-bit and 64-bit writes execute

in a single AHB data phase cycle allowing for zero wait states on back to back writes of these sizes.

Depending on the size and address of the write, one or both array chip selects are asserted (see Table 19-5).

345

addr y

addr z

addr z+4

nonseq

seq

idle

long

word

data y

data z

data z+4

addr y

addr z

addr z+4

2'b00

2'b01

2'b10

2'b11

data y

data z

data z+4

hclk

haddr

htrans

hwrite

hsize

hready

hrdata

hwdata

pram_addr

pram_we

pram_cs_b

pram_rdata

pram_wdata

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