MAC7200 datasheet(467/976 Pages) FREESCALE

467 / 976 page

Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

389

If, during the data phase of a write, a read is requested on the AHB, the write is registered in the late write

buffer allowing the read to take place without a wait state. The exception occurs when the read address

matches the write address (see Section 19.2.3.6, “Late Write Hits”). The valid buffered or late write data

is stored on the next available array address phase.

This behavior is shown in Figure 19-6. Cycle 1 shows the AHB write address phase to address ’y’. In

cycle 2, a read request to address ’z’ takes priority over the write and is executed to the array while the

write data is stored to the late write buffer. The read in cycle 3 again takes precedence and the late write

buffer is held. In cycle 4, the late write is stored. The controller executes in this way for both 32 and 64-bit

sizes.

Figure 19-5. 32/64-bit writes with reads

Back to back 32/64-bit writes execute slightly differently in that the write in the AHB data phase is not

stored to the late write buffer. Rather, the write data is stored directly to the array in the same cycle in

which it is valid on the AHB. Figure 19-7 shows the write to ’addr y’ in cycle 2 executing to the array in

the same cycle as the data is valid on the AHB. In addition, the write to ’addr y+32’ in cycle 3 is registered

in the late write buffer since it is not followed by a 32 or 64-bit write transfer.

123456

addr y

addr z

addr z+4

addr y+4

nonseq

seq

nonseq

idle

word

data z

data z+4

data y

data y+4

addr z

addr z+4

addr y

addr y+4

2'b11

2'b10

2'b01

2'b10

2'b11

2'b01

data z

data z+4

data y

data y+4

data y

data y+4

hclk

haddr

htrans

hwrite

hsize

hready

hrdata

hwdata

pram_addr

pram_we

pram_cs_b

pram_rdata

pram_wdata

late write buffer

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