MAC7200 datasheet(481/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

403

Chapter 21

IPI Subsystem (IPSS)

The IPI Subsystem (IPSS) is responsible for connecting all Peripheral Bus peripherals to the AIPS module.

21.1

Bus Abort handling

Bus aborts on the Peripheral Bus fall into one of two categories:

•

Bus aborts produced by peripherals due to an illegal access. This type of abort may be masked with

the REG_ABORT bit in the ERROR register in the SSM module.

•

Bus aborts produced accesses to an empty peripheral slot. These aborts are OR’d together and

gated by the PER_ABORT bit in the ERROR register in the SSM module.

21.2

Peripheral Bus Peripheral Clock Frequencies

21.3

IPSS Differences from MAC71xx

•

Bus aborts for empty peripheral slots may now be masked using a bit in the SSM

•

Following peripherals now run at full system speed (was 1/2 system speed on MAC71x1)

—ATD_A

— DSPI_A/B/C

Half Speed

Full Speed

CAN_A/B

ATD_A

PIT

DSPI_A/B/C

eMIOS

FlexBus (registers and protocol)

SCI_A/B

MCM

Flash (registers only)

INTC

SSM

DMA2

CRG (registers only)

AIPS (registers)

DMA Channel Mux

PIM

IIC

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