MAC7200 datasheet(546/976 Pages) FREESCALE

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Memory Map and Register Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

468

Freescale Semiconductor

26.8.2.2

PIT Current RTI / Timer Values (TVAL0–10)

These registers indicate the current timer position. In the case of the RTI, this will show a value which is

several cycles old, since it originates from a potentially different clock domain.

Address Offset: 0x04–0x2B

Access: User read/write

TSV31

TSV30

TSV29

TSV28

TSV27

TSV26

TSV25

TSV24

Reset

000

0000

TSV23

TSV22

TSV21

TSV20

TSV19

TSV18

TSV17

TSV16

Reset

000

0000

TSV15

TSV14

TSV13

TSV12

TSV11

TSV10

TSV9

TSV8

Reset

000

0000

5432

TSV7

TSV6

TSV5

TSV4

TSV3

TSV2

TSV1

TSV0

Reset

000

0000

Figure 26-3. PIT Timer Load Value Registers (TLVAL1–10)

Table 26-6. TLVAL1–10 Field Descriptions

Field

Description

31–0

TSVn

Time Start Value Bits. These bits set the timer start value. The timer will count down until it reaches 0,

then it will generate an interrupt and load this register value again. Writing a new value to this register will

not restart the timer, instead the value will be loaded once the timer expires. To abort the current cycle

and start a timer period with the new value, the timer must be disabled and enabled again (see

Figure 26-9).

NOTE: For the RTI, the timer should not be set to a value lower than 32 cycles, otherwise interrupts may

be lost, as it takes several cycles to clear the RTI interrupt. For the other timers, this limit does not apply,

however there will be practical limits, since the processor will require several cycles to service an interrupt.

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