MAC7200 datasheet(549/976 Pages) FREESCALE

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Memory Map and Register Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

471

26.8.2.4

PIT Interrupt Enable Register (PITINTEN)

This register enables PIT interrupts.

Address Offset:

0x100

Access: User read/write (write to clear)

00000000

Reset

00000000

Reset

00000000

Reset

00000000

765

43210

000

TIF4

TIF3

TIF2

TIF1

RTIF

Reset

00000000

Figure 26-6. APIT Interrupt Flags Register (PITFLG)

Table 26-9. PITFLG Field Desciptions

Field

Description

31–5

Reserved, should be cleared.

4–1

TIFn

Real Time Interrupt Flags for Timer 1–4. TIFn is set to 1 at the end of the timer period. This flag can be

cleared only by writing a 1. Writing a 0 has no effect. If enabled (TIEx = 1 and ISELx = 1), TIFn causes

an interrupt request.

0 Time-out has not yet occurred

1 Time-out has occurred

RTIF

Real Time Interrupt Flag. RTIF is set to 1 at the end of the RTI period. This flag can be cleared only by

writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.

0 RTI time-out has not yet occurred

1 RTI time-out has occurred

MAC7200 Datasheet(PDF) 549 Page - Freescale Semiconductor, Inc

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