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MAC7200 Datasheet(PDF) 555 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 555 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
477
Figure 26-13. Dynamically Setting a New Load Value
Four of the timers and the RTI support interrupts. The RTI is used for system wakeup only. The other
interrupts are general-purpose.
26.9.1.2
Debug Mode
In Debug Mode the timers will be frozen - this is intended to aid software development, allowing the
developer to halt the processor, investigate the current state of the system (e.g. the timer values) and then
continue the operation.
26.9.2
Interrupts
The interrupts generated by the PIT are listed in Figure 26-14. Refer to the MCU specification for related
vector addresses and priorities.
26.9.2.1
Real Time Interrupt
The PIT_RTI generates a real time interrupt when the selected interrupt time period elapses. The RTI
interrupt is disabled locally by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to 1
when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
Since the RTI operates on the oscillator clock, it can be used for periodic wakeup from WAIT mode
providede the CRG’s PRE bit is set to 1 and the RTI interrupt is enabled. It can also be used to generate a
general purpose interrupt.
26.9.2.2
Timer Interrupts
The PIT can also generate timer interrupts on the first four timer channels, when the timer’s selected
interrupt period elapses. Timer interrupts are disabled locally by setting the TIE bits to zero. The timer
interrupt flags (TIF) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by
Table 26-14. PIT Interrupt Vectors
Interrupt Source
Local Enable
Real time interrupt
RTIE
Timer Interrupts
TIE[4:1]
p1
p1
Timer Enabled
New Start
Value p2 set
p1
p2
Start Value = p1
p2
Trigger
Event



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