MAC7200 datasheet(556/976 Pages) FREESCALE

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Initialization and Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

478

Freescale Semiconductor

writing a 1 to that TIF bit. To activate a timer interrupt it must also be switched from trigger mode into

interrupt mode, using the PITINTSEL register.

The timer interrupts are general-purpose interrupts.

26.10 Initialization and Application Information

26.10.1 Example Configuration

In the example configuration:

•

the PIT clock has a frequency of 50 MHz

•

the RTI clock has a frequency of 10 MHz

•

the RTI timer shall be set up to create a wakeup interrupt every 500 ms

•

timer 1 shall create an interrupt every 5.12 ms

•

timer 8 shall create a trigger event every 30 ms.

First the PIT module needs to be activated by writing a 0 to the MDIS bit in the PITCTRL register.

The 50 MHz clock frequency equates to a clock period of 20 ns and the 10 MHz frequency equates to a

clock period of 100 ns. Therefore the RTI timer needs to trigger every 500 ms/100 ns = 5000000 cycles,

timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 8 every 30 ms/20 ns = 1500000

cycles. The value for the TVAL register trigger would be calculated as (period / clock period) -1.

This means that TVAL0 will be written with 004C4B3F hex, TVAL1 with 00003E7FF hex and TVAL8

with 0016E35F hex.

To generate the interrupt, the interrupt line must be enabled by writing a 1 to the RTIE bit in the PITINTEN

for trigger events. To start the RTI, PEN0 in the PIT Timer Enable register 0 (PITEN0) is set.

The interrupt for Timer 1 is enabled by setting TIE1 in the PITINTEN register and the Interrupt/DMA

selector ISEL1 (in PITINTSEL) is set to 1. The timer is started by writing a 1 to bit PEN1 in the PITEN

Timer 8 shall be used only for triggering. Only timers 0–4 have interrupt capability. Therefore Timer 8 is

started by writing a 1 to bit PEN8 in the PITEN1 register.

It is also possible to setup all timers and start them simultaneously by writing to the PITEN registers.

However the RTI still cannot start in synchronisation as it is running on a separate clock.

The following example code matches the described setup:

// turn on PIT

PIT_REG_P->pit_CTRL = 0x00;

// RTI

CRG_REG_P->crg_CTL

|= 1<<2;

// Set RTI bit in CLKSEL

PIT_REG_P->pit_TLVAL0 = 0x004C4B3F; // setup RTI for 5000000 cycles

PIT_REG_P->pit_INTEN = 0x00000001; // let RTI generate interrupts

// writing INTSEL is unnecessary

PIT_REG_P->pit_EN |= 1<<0; // start RTI

MAC7200 Datasheet(PDF) 556 Page - Freescale Semiconductor, Inc

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