MAC7200 datasheet(630/976 Pages) FREESCALE

Part #	MAC7200

Description	MAC7200 Microcontroller Family Reference Manual

PDF	976 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

552

Freescale Semiconductor

The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown

in the scl2tap column of Table 29-5. All subsequent tap points are separated by 2IBC5-3 as shown in the

tap2tap column in Table 29-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used

to determine the delay from the falling edge of SCL to the change of state of SDA i.e. the SDA hold time.

Figure 29-6. SDA Hold Time

Figure 29-7. SCL Divider and SDA Hold

The equation used to generate the divider values from the IBFD bits is:

SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}

Eqn. 29-1

110

111

Table 29-6. I-Bus Tap and Prescale Values

IBC2-0

SCL Tap

(clocks)

SDA Tap

(clocks)

SCL Divider

SDA Hold

SCL

SDA

SCL

START condition

STOP condition

SCL Hold(start)

SCL Hold(stop)

MAC7200 Datasheet(PDF) 630 Page - Freescale Semiconductor, Inc