MAC7200 datasheet(627/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

549

29.4.1

Enabling the

I2C Module

Before the I2C module can be used, it must be explicitly enabled by clearing the IBDIS/MDIS bit in the

ICBR register in the I2C module. If Open Drain functionality is required on the I2C bus, this functionality

must be enabled in the Port Integration Module (PIM).

NOTE

Note that, unlike in other peripherals, clearing the IBDIS bit causes a reset

of all other I2C registers.

29.5

Memory Map/Register Definition

This section provides a detailed description of all memory-mapped registers in the I2C module.

29.5.1

Module Memory Map

The memory map for the I2C module is given below in Table 29-1. The total address for each register is

the sum of the base address for the I2C module and the address offset for each register.

NOTE

Please see Chapter 9, “Device Memory Map” for base address of this

module.

All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned

to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the IBDF

performing a 16-bit access to Base + 0x001 is illegal.

Table 29-1. Module Memory Map

Address

Size

Access

Mode1

1. U = User Mode, S = Supervisor Mode, A = All (No restrictions)

Base + 0x00

I2C Bus Address Register (IBAD)

R/W

Base + 0x01

I2C Bus Frequency Divider Register (IBFD)

R/W

Base + 0x02

I2C Bus Control Register (IBCR)

R/W

Base + 0x03

I2C Bus Status Register (IBSR)

R/W

Base + 0x04

I2C Bus Data I/O Register (IBDR)

R/W

Base + 0x05

I2C Bus Interrupt Config Register (IBIC)

R/W

Base + 0x06

Unused

Base + 0x07

Unused

Base + 0x08 –

Base + 0x3FFF

Reserved

See Note 2

2. If enabled at the SoC level, reads or writes to these registers will cause bus aborts. Refer to the System Services Module

documentation for more details.

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