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MAC7200 Datasheet(PDF) 626 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 626 Page - Freescale Semiconductor, Inc |
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626 / 976 page  I2C Module Implementation MAC7200 Microcontroller Family Reference Manual, Rev. 2 548 Freescale Semiconductor • Memory Map: 32-bit peripheral with 8 register bytes, byte/halfword/word addressable • Two wire bi-directional serial bus for on board communications. • Multi-master operation. • Software-programmable for one of 256 different serial clock frequencies. • Software-selectable acknowledge bit. • Interrupt-driven byte-by-byte data transfer. • Arbitration-lost interrupt with automatic mode switching from master to slave. • Calling address identification interrupt. • Start and stop signal generation/detection. • Repeated START signal generation. • Acknowledge bit generation/detection • Bus-busy detection. • Two DMA request lines to receive and transmit data Features currently not supported: • No support for general call address • Not compliant to ten-bit addressing 29.1.4 Modes of Operation The I2C module operates in all MAC7200 modes. • Run Mode This is the basic mode of operation. • Doze Mode This is a low-power mode that allows the system to turn off the clock depending on the state of an internal bit. The I2C block will allow this state to be entered only when there are no active transfers on the bus. Note that a transfer is defined as any active data between valid I2C Start and I2C Stop conditions. 29.2 I2C Module Implementation The I2C on the MAC72xx is identical to the I2C (IIC) on the MAC71xx family of devices. 29.3 External Signal Description The Inter-Integrated Circuit (I2C) module has two external pins, SCL and SDA. Refer to Table 4-1 and Section 4.3, “Detailed Signal Descriptions” for detailed descriptions of these signals. 29.4 I2C Module Differences from MAC71xx • Fixed MUCts01649 (Write on bus abort still writes register) |
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