MAC7200 datasheet(628/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

550

Freescale Semiconductor

29.5.2

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated figure number. Details of register bit and field function follow the register

diagrams, in bit order.

29.5.2.1

I2C Address Register

This register contains the address the I2C Bus will respond to when addressed as a slave; note that it is not

the address sent on the bus during the address transfer.

29.5.2.2

I2C Frequency Divider Register

Always

Always

R/W

bit

BIT

Read-

only bit

BIT

Write-

only bit

Write 1

to clear

BIT Self-clear

bit

N/A

BIT

w1c

BIT

Figure 29-3. Key to Register Fields

Offset 0x00000

Access: Read/write any time

321

ADR

Reset

000

Figure 29-4. I2C Bus Address Register (IBAD)

Table 29-2. IBAD Field Descriptions

Field

Description

7–1

ADR

Slave Address. Specific slave address to be used by the I2C Bus module.

Note: The default mode of I2C Bus is slave mode for an address match on the bus.

Reserved, should be cleared; will always read 0.

Offset 0x0001

Access: Read/write any time

321

IBC

Reset

000

Figure 29-5. I2C Bus Frequency Divider Register (IBFD)

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