MAC7200 datasheet(699/976 Pages) FREESCALE

699 / 976 page

Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

621

30.13.5 Calculation of FIFO Pointer Addresses

The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid

entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.

The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is

the Transmit Next Pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the Pop Next Pointer

(POPNXTPTR). Figure 30-25 illustrates the concept of first-in and last-in FIFO entries along with the

FIFO Counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.

See Section 30.12.3.4, “Transmit First In First Out (TX FIFO) Buffering Mechanism,” and

Section 30.12.3.5, “Receive First In First Out (RX FIFO) Buffering Mechanism,” for details on the FIFO

operation.

Table 30-33. Oak Family QSPI Compatibility with the DSPI

Oak Family Control Bits

DSPI Corresponding Control Bits

Corresponding DSPI_CTAR Register Configuration

BITSE CTAS[2]DT

CTAS[1]

DSCK

CTAS[0]

DSPI_CTARx

FMSZ

PDT

PCSSCK

CSSCK

1111

0011

0000

1111

0011

user

1111

user1

1. Selected by user

user

0000

1111

user

0011

0000

user

0011

user

0000

user

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