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MAC7200 Datasheet(PDF) 698 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 698 Page - Freescale Semiconductor, Inc |
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698 / 976 page ![]() Initialization/Application Information MAC7200 Microcontroller Family Reference Manual, Rev. 2 620 Freescale Semiconductor 30.13.4 Oak Family Compatibility with the DSPI Table 30-33 shows the translation of commands written to the TX FIFO command halfword with commands written to the Command Ram of the Oak family QSPI. The table illustrates how to configure the DSPI_CTAR registers to match the default cases for the possible combinations of the Oak Family Control Bits in its Command RAM. The defaults for the Oak Family are based on a system clock of 40MHz. All delay variables below will generate the same delay, or as close a possible, from the DSPI 100MHz system clock that an Oak Family part would generate from its 40MHz system clock. For other system clock frequencies, the customer can recompute the values using Delay Settings. • For BITSE = 0 → 8 bits per transfer • For DT = 0 → 0.425μs delay: For this value, the closest value in the DSPI is 0.480μs • For DSCK = 0 → 1/2 SCK period: For this value, the value for the DSPI is 20ns Table 30-32. Delay Values Delay Prescaler Values 1357 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 μs 32 320.0 ns 960.0 ns 1.6 μs2.2 μs 64 640.0 ns 1.9 μs3.2 μs4.5 μs 128 1.3 μs3.8 μs6.4 μs9.0 μs 256 2.6 μs7.7 μs 12.8 μs 17.9 μs 512 5.1 μs 15.4 μs 25.6 μs 35.8 μs 1024 10.2 μs 30.7 μs 51.2 μs 71.7 μs 2048 20.5 μs 61.4 μs 102.4 μs 143.4 μs 4096 41.0 μs 122.9 μs 204.8 μs 286.7 μs 8192 81.9 μs 245.8 μs 409.6 μs 573.4 μs 16384 163.8 μs 491.5 μs 819.2 μs 1.1 ms 32768 327.7 μs 983.0 μs 1.6 ms 2.3 ms 65536 655.4 μs 2.0 ms 3.3 ms 4.6 ms |
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