MAC7200 datasheet(696/976 Pages) FREESCALE

696 / 976 page

Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

618

Freescale Semiconductor

TX FIFO. Clearing either of the FIFOs will not have any affect in the Module Disable Mode. Changes to

the DIS_TXF and DIS_RXF fields of the DSPI_MCR will not have any affect in the Module Disable

Mode. In the Module Disable Mode, all status bits and register flags in the DSPI will return the correct

values when read, but writing to them will have no affect. Writing to the DSPI_TCR during Module

Disable Mode will not have any affect. Interrupt and DMA request signals cannot be cleared while in the

Module Disable Mode.

30.12.8.3 Signal Gating

The DSPI’s module enable signal is used to gate signals such as address, byte enable, read/write and data.

This prevents toggling signals from propagating through parts of the DSPI’s combinational logic and

consuming power unless it is a DSPI access. The module enable signal can also be used to gate the clock

(ipg_clk_s) to the memory-mapped logic.

30.13 Initialization/Application Information

30.13.1 How to Change Queues

This section presents an example of how to change queues for the DSPI. The queues are not part of the

DSPI, but the DSPI includes features in support of queue management. Queues are primarily supported in

SPI Configuration.

1. The last command word from a queue is executed. The EOQ bit in the command word is set to

indicate to the DSPI that this is the last entry in the queue.

2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ

flag (EOQF) in the DSPI_SR is set.

3. The setting of the EOQF flag will disable both serial transmission, and serial reception of data,

putting the DSPI in the STOPPED state. The TXRXS bit is negated to indicate the STOPPED state.

4. The DMA will continue to fill TX FIFO until it is full or step 5 occurs.

5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned

to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in

the DMA Controller.

6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the

RXCNT in DSPI_SR or by checking RFDF in the DSPI_SR after each read operation of the

DSPI_POPR.

7. Modify DMA descriptor of TX and RX channels for "new" queues

8. Flush TX FIFO by writing a ‘1’ to the CLR_TXF bit in the DSPI_MCR, Flush RX FIFO by writing

a ‘1’ to the CLR_RXF bit in the DSPI_MCR.

9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new

queue or via CPU writing directly to SPI_TCNT field in the DSPI_TCR.

10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the

DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.

11. Enable serial transmission and serial reception of data by clearing the EOQF bit.

MAC7200 Datasheet(PDF) 696 Page - Freescale Semiconductor, Inc