MAC7200 datasheet(693/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

615

•

Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode.

Figure 30-23 shows timing diagram for Continuous SCK format with Continuous Selection enabled.

Figure 30-23. Continuous SCK Timing Diagram (CONT=1)

30.12.7 Interrupts/DMA Requests

The DSPI has four conditions that can only generate interrupt requests and two conditions that can

generate interrupt or DMA request. Table 30-30 lists the six conditions.

Each condition has a flag bit in the DSPI Status Register (DSPI_SR) and an Request Enable bit in the DSPI

DMA/Interrupt Request Select and Enable Register (DSPI_RSER). The TX FIFO Fill Flag (TFFF) and

RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests depending on the TFFF_DIRS

and RFDF_DIRS bits in the DSPI_RSER.

30.12.7.1 End of Queue Interrupt Request

The End of Queue Request indicates that the end of a transmit queue is reached. The End of Queue Request

is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the

DSPI_RSER is asserted.

Table 30-30. Interrupt and DMA Request Conditions

Condition

Flag

Interrupt

DMA

End of Queue (EOQ)

EOQF

TX FIFO Fill

TFFF

Transfer Complete

TCF

TX FIFO Underflow

TFUF

RX FIFO Drain

RFDF

RX FIFO Overflow

RFOF

SCK

PCS

SCK

Master SOUT

Master SIN

(CPOL = 0)

(CPOL = 1)

transfer 1

transfer 2

MAC7200 Datasheet(PDF) 693 Page - Freescale Semiconductor, Inc

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