MAC7200 datasheet(692/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

614

Freescale Semiconductor

30.12.6 Continuous Serial Communications Clock

The DSPI provides the option of generating a continuous SCK signal for slave peripherals that require a

continuous clock.

Continuous SCK is enabled by setting the CONT_SCKE bit in the DSPI_MCR. Continuous SCK is valid

in all configurations.

Continuous SCK is only supported for CPHA=1. Setting CPHA=0 will be ignored if the CONT_SCKE bit

is set. Continuous SCK is supported for Modified Transfer Format.

Clock and transfer attributes for the Continuous SCK mode are set according to the following rules:

•

CTAR0 shall be used initially. At the start of each SPI frame transfer, the CTAR specified by the

CTAS for the frame shall be used.

•

The currently selected CTAR shall remain in use until the start of a frame with a different CTAR

specified, or the Continuous SCK mode is terminated.

It is recommended that the baud rate is the same for all transfers made while using the Continuous SCK.

Switching clock polarity between frames while using Continuous SCK can cause errors in the transfer.

Continuous SCK operation is not guaranteed if the DSPI is put into the External Stop Mode or Module

Disable Mode.

Enabling Continuous SCK disables the PCS to SCK delay and the Delay after Transfer (TDT) is fixed at

one TSCK cycle. Figure 30-22 shows timing diagram for Continuous SCK format with Continuous

Selection disabled.

Figure 30-22. Continuous SCK Timing Diagram (CONT=0)

If the CONT bit in the TX FIFO entry is set, PCS remains asserted between the transfers . Under certain

conditions, SCK can continue with PCS asserted, but with no data being shifted out of SOUT (SOUT

pulled high). This can cause the slave to receive incorrect data. Those conditions include:

•

Continuous SCK with CONT bit set, but no data in the transmit FIFO.

•

Continuous SCK with CONT bit set and entering STOPPED state (refer to Section 30.12.2, “Start

and Stop of DSPI Transfers”).

tDT

SCK

PCS

SCK

Master SOUT

Master SIN

(CPOL = 0)

(CPOL = 1)

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