MAC7200 datasheet(688/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

610

Freescale Semiconductor

Figure 30-17. DSPI Transfer Timing Diagram (MTFE=0, CPHA=1, FMSZ=8)

The master initiates the transfer by asserting the PCS signal to the slave. After the tCSC delay has elapsed,

the master generates the first SCK edge and at the same time places valid data on the master SOUT pin.

The slave responds to the first SCK edge by placing its first data bit on its slave SOUT pin.

At the second edge of the SCK the master and slave sample their SIN pins. For the rest of the frame the

master and the slave change the data on their SOUT pins on the odd-numbered clock edges and sample

their SIN pins on the even-numbered clock edges. After the last clock edge occurs a delay of tASC is

inserted before the master negates the PCS signal. A delay of tDT is inserted before a new frame transfer

can be initiated by the master.

30.12.5.3 Modified Transfer Format (MTFE = 1, CPHA = 0)

In this Modified Transfer Format both the Master and the Slave sample later in the SCK period than in

Classic SPI mode to allow for delays in device pads and board traces. These delays become a more

significant fraction of the SCK period as the SCK period decreases with increasing baud rates.

The Master and the Slave places data on the SOUT pins at the assertion of the PCS signal. After the PCS

to SCK delay has elapsed the first SCK edge is generated. The Slave samples the Master SOUT signal on

every odd numbered SCK edge. The Slave also places new data on the Slave SOUT on every odd

numbered clock edge.

tCSC

tDT

SCK

MSB first (LSBFE = 0):

LSB first (LSBFE = 1):

MSB

LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

tCSC = PCS to SCK delay

tDT = Delay after Transfer (minimum CS negation time)

(CPOL = 0)

(CPOL = 1)

tASC

Master SOUT/

Master SIN/

Slave SIN

Slave SOUT

10 11 12 13 14

15 16

PCSx/SS

Master and Slave

Sample

tASC = After SCK delay

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