MAC7200 datasheet(687/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

609

Figure 30-16. DSPI Transfer Timing Diagram (MTFE=0, CPHA=0, FMSZ=8)

The master initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate

peripheral chip select signals to the slave device. The slave responds by placing its first data bit on its

SOUT pin. After the tCSC delay has elapsed, the master outputs the first edge of SCK. This is the edge used

by the master and slave devices to sample the first input data bit on their serial data input signals. At the

second edge of the SCK the master and slave devices place their second data bit on their serial data output

signals. For the rest of the frame the master and the slave sample their SIN pins on the odd-numbered clock

edges and changes the data on their SOUT pins on the even-numbered clock edges. After the last clock

edge occurs a delay of tASC is inserted before the master negates the PCS signals. A delay of tDT is inserted

before a new frame transfer can be initiated by the master.

30.12.5.2 Classic SPI Transfer Format (CPHA = 1)

This transfer format shown in Figure 30-17 is used to communicate with peripheral SPI slave devices that

require the first SCK edge before the first data bit becomes available on the slave SOUT pin. In this format

the master and slave devices change the data on their SOUT pins on the odd-numbered SCK edges and

sample the data on their SIN pins on the even-numbered SCK edges

tCSC

SCK

Master and Slave

PCSx/SS

SCK

MSB first (LSBFE = 0):

LSB first (LSBFE = 1):

MSB

LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

Master SOUT/

Master SIN/

tDT tCSC

tCSC = PCS to SCK delay

tDT = Delay after Transfer (Minimum CS idle time)

(CPOL = 0)

(CPOL = 1)

tASC

Slave SIN

Slave SOUT

10 11 12 13

15 16

Sample

tASC = After SCK delay

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