MAC7200 datasheet(684/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

606

Freescale Semiconductor

30.12.4.1 Baud Rate Generator

The Baud Rate is the frequency of the Serial Communication Clock (SCK). The system clock is divided

by a prescaler (PBR) and scaler (BR) to produce SCK with the possibity of halving the scaler division. The

DBR, PBR and BR fields in the DSPI_CTAR registers select the frequency of SCK by the formula in the

BR[3:0] field description. Table 30-24 shows an example of how to compute the baud rate.

30.12.4.2 PCS to SCK Delay (tCSC)

The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge. See

Figure 30-16 for an illustration of the PCS to SCK delay. The PCSSCK and CSSCK fields in the

DSPI_CTARx registers select the PCS to SCK delay by the formula in the CSSCK[3:0] bit description.

Table 30-25 shows an example of how to compute the PCS to SCK delay.

30.12.4.3 After SCK Delay (tASC)

The After SCK Delay is the length of time between the last edge of SCK and the negation of PCS. See

Figure 30-16 and Figure 30-17 for illustrations of the After SCK delay. The PASC and ASC fields in the

DSPI_CTARx registers select the After SCK Delay by the formula in the ASC[3:0] field description..

Table 30-26 shows an example of how to compute the After SCK delay.

30.12.4.4 Delay after Transfer (tDT)

The Delay after Transfer is the length of time between negation of the PCS signal for a frame and the

assertion of the PCS signal for the next frame. See Figure 30-16 for an illustration of the Delay after

Transfer. The PDT and DT fields in the DSPI_CTARx registers select the Delay after Transfer by the

formula in the DT[3:0] field description. Table 30-27 shows an example of how to compute the Delay after

Transfer.

Table 30-24. Baud Rate Computation Example

PBR

Prescaler

Scaler

DBR

Fsys

Baud Rate

0b00

0b0000

100 MHz

25 Mb/s

0b00

0b0000

20 MHz

10 Mb/s

Table 30-25. PCS to SCK Delay Computation Example

PCSSCK

Prescaler

CSSCK

Scaler

Fsys

PCS to SCK Delay

0b01

0b0100

100 MHz

0.96 us

Table 30-26. After SCK Delay Computation Example

PASC

Prescaler

ASC

Scaler

Fsys

After SCK Delay

0b01

0b0100

100 MHz

0.96 us

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