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MAC7200 Datasheet(PDF) 685 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 685 Page - Freescale Semiconductor, Inc |
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685 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 607 30.12.4.5 Peripheral Chip Select Strobe Enable (PCSS) The PCSS signal provides a delay to allow the PCS signals to settle after transitioning thereby avoiding glitches. When the DSPI is in Master Mode and PCSSE bit is set in the DSPI_MCR, PCSS provides a signal for an external demultiplexer to decode the PCS[0] -PCS[4] and PCS[6] -PCS[7] signals into as many as 128 glitch-free PCS signals. Figure 30-15 shows the timing of the PCSS signal relative to PCS signals. Figure 30-15. Peripheral Chip Select Strobe Timing The delay between the assertion of the PCS signals and the assertion of PCSS is selected by the PCSSCK field in the DSPI_CTAR based on the following formula: Eqn. 30-6 At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the DSPI_CTAR based on the following formula: Eqn. 30-7 Table 30-28 shows an example of how to compute the tpcssck delay. Table 30-29 shows an example of how to compute the tpasc delay. The PCSS signal is not supported when Continuous Serial Communication SCK is enabled (CONT_SCKE=1). Table 30-27. Delay after Transfer Computation Example PDT Prescaler DT Scaler Fsys Delay after Transfer 0b01 3 0b1110 32768 100 MHz 0.98 ms Table 30-28. Peripheral Chip Select Strobe Assert Computation Example PCSSCK Prescaler Fsys Delay before Transfer 0b11 7 100 MHz 70.0 ns Table 30-29. Peripheral Chip Select Strobe Negate Computation Example PASC Prescaler Fsys Delay after Transfer 0b11 7 100 MHz 70.0 ns t PCSSCK PCSS PCSx t PASC t PCSSCK 1 f SYS ---------- PCSSCK × = t PASC 1 f SYS ---------- PASC × = |
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