MAC7200 datasheet(682/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

604

Freescale Semiconductor

30.12.3.4 Transmit First In First Out (TX FIFO) Buffering Mechanism

The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds

from one to sixteen words, each consisting of a command field and a data field. The number of entries in

the TX FIFO is SoC specific. SPI commands and data are added to the TX FIFO by writing to the DSPI

PUSH TX FIFO Register (DSPI_PUSHR). TX FIFO entries can only be removed from the TX FIFO by

being shifted out or by flushing the TX FIFO.

The TX FIFO Counter field (TXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of

valid entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data

is transferred into the shift register from the TX FIFO.

The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the next transfer. The

TXNXTPTR contains the positive offset from DSPI_TXFR0 in number of 32-bit registers. For example,

TXNXTPTR equal to two means that the DSPI_TXFR2 contains the SPI data and command for the next

transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the

shift register.

30.12.3.4.1

Filling the TX FIFO

Host software or other intelligent blocks can add (push) entries to the TX FIFO by writing to the

DSPI_PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in the DSPI_SR is set. The

TFFF bit is cleared when TX FIFO is full and the DMA controller indicates that a write to DSPI_PUSHR

is complete or by host software writing a ‘1’ to the TFFF in the DSPI_SR. The TFFF can generate a DMA

request or an interrupt request. See Section 30.12.7.2, “Transmit FIFO Fill Interrupt or DMA Request,”

for details.

The DSPI ignores attempts to push data to a full TX FIFO, i.e. the state of the TX FIFO is unchanged. No

error condition is indicated.

30.12.3.4.2

Draining the TX FIFO

The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are

transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the

TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO Counter

is decremented by one. At the end of a transfer, the TCF bit in the DSPI_SR is set to indicate the

completion of a transfer. The TX FIFO is flushed by writing a ‘1’ to the CLR_TXF bit in DSPI_MCR.

If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is empty,

the Transmit FIFO Underflow Flag (TFUF) in the slave’s DSPI_SR is set. See Section Section 30.12.7.4,

“Transmit FIFO Underflow Interrupt Request,” for details.

30.12.3.5 Receive First In First Out (RX FIFO) Buffering Mechanism

The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds from one to

sixteen received SPI data frames. The number of entries in the RX FIFO is SoC specific. SPI data is added

to the RX FIFO at the completion of a transfer when the received data in the shift register is transferred

into the RX FIFO. SPI data are removed (popped) from the RX FIFO by reading the DSPI POP RX FIFO

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