MAC7200 datasheet(679/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

601

30.12.1.1 Master Mode

In Master Mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus

master when the MSTR bit in the DSPI_MCR is set. The Serial Communications Clock (SCK) is

controlled by the Master DSPI.

Master Mode transfer attributes are controlled by the SPI command in the current TX FIFO entry. The

CTAS field in the SPI command selects which of the eight DSPI_CTAR registers will be used to set the

transfer attributes. Transfer attribute control is on a frame by frame basis. See Section 30.12.3, “Serial

Peripheral Interface (SPI) Configuration,” for more details.

30.12.1.2 Slave Mode

In Slave Mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave

when the MSTR bit in the DSPI_MCR register is negated. The DSPI slave is selected by a bus master by

having the slave’s SS asserted.. In Slave Mode the SCK is provided by the bus master. All transfer

attributes are controlled by the bus master but clock polarity, clock phase and numbers of bits to transfer

must still be configured in the DSPI slave for proper communications.

In SPI Slave Mode the slave transfer attributes are set in the DSPI_CTAR0. The DSPI in Slave Mode

transfers data MSB first. The LSBFE field of the associated CTAR is ignored.

30.12.1.3 Module Disable Mode

The Module Disable Mode is used for MCU power management. The clock to the non-memory mapped

logic in the DSPI can be stopped while in Module Disable Mode.The DSPI enters the Module Disable

Mode when the MDIS bit in DSPI_MCR is set or when a request for the DSPI to enter Doze Mode is

asserted by an external controller while the DOZE bit in the DSPI_MCR is asserted. Logic external to the

DSPI is needed to implement the Module Disable Mode. See Section 30.12.8, “Power Saving Features,”

for more details on the Module Disable Mode.

30.12.1.4 External Stop Mode

The DSPI will not acknowledge the request to enter External Stop Mode until it has reached a frame

boundary. When the DSPI has reached a frame boundary it will halt all operations and indicate that it is

ready to have its clocks shut off. The DSPI exits External Stop Mode and resumes normal operation once

the clocks are turned on. Serial communications or register accesses made while in External Stop Mode

are ignored even if the clocks have not been shut off yet. See Section 30.12.8, “Power Saving Features,”

for more details on the External Stop Mode.

30.12.1.5 Debug Mode

The Debug Mode is used for system development and debugging. If the SoC enters Debug Mode while

the FRZ bit in the DSPI_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the

SoC enters Debug Mode while the FRZ bit is negated, the DSPI behavior is unaffected and remains

dictated by the block-specific mode and configuration of the DSPI. The DSPI enters Debug Mode when a

debug request is asserted by an external controller. See Figure 30-13 for a state diagram.

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