MAC7200 datasheet(675/976 Pages) FREESCALE

675 / 976 page

Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

597

30.11.2.7 DSPI POP RX FIFO Register (DSPI_POPR)

The DSPI_POPR provides a means to read the RX FIFO. See Section 30.12.3.5, “Receive First In First

Out (RX FIFO) Buffering Mechanism,” for a description of the RX FIFO operations. Eight or sixteen bit

read accesses to the DSPI_POPR will read from the RX FIFO and update the counter and pointer.

Table 30-19. DSPI_PUSHR Field Descriptions

Field

Descriptions

CONT

Continuous Peripheral Chip Select Enable. The CONT bit selects a Continuous Selection Format. The bit

is used in SPI Master Mode. The bit enables the selected PCS signals to remain asserted between

transfers. See Section 30.12.5.5, “Continuous Selection Format,” for more information.

0 Return Peripheral Chip Select signals to their inactive state between transfers

1 Keep Peripheral Chip Select signals asserted between transfers

30–28

CTAS[2:0]

Clock and Transfer Attributes Select. The CTAS field selects which of the DSPI_CTAR register is used to

set the transfer attributes for the associated SPI frame. The field is only used in SPI Master Mode. In SPI

Slave Mode DSPI_CTAR0 is used. The table below shows how the CTAS values map to the DSPI_CTAR

registers. The number of DSPI_CTAR registers is implementation specific.

EOQ

End Of Queue. The EOQ bit provides a means for host software to signal to the DSPI that the current SPI

transfer is the last in a queue. At the end of the transfer the EOQF bit in the DSPI_SR is set.

0 The SPI data is not the last data to transfer

1 The SPI data is the last data to transfer

CTCNT

Clear SPI_TCNT. The CTCNT provides a means for host software to clear the SPI transfer counter. The

CTCNT bit clears the SPI_TCNT field in the DSPI_TCR register. The SPI_TCNT field is cleared before

transmission of the current SPI frame begins.

0 Do not clear SPI_TCNT field in the DSPI_TCR

1 Clear SPI_TCNT field in the DSPI_TCR

23–16

PCSx

Peripheral Chip Select 0–7. The PCS bits select which PCS signals will be asserted for the transfer.

0 Negate the PCS[x] signal

1 Assert the PCS[x] signal

15–0

TXDATA[15:0]

Transmit Data. The TXDATA field holds SPI data to be transferred according to the associated SPI

command.

CTAS

Use Clock and Transfer

Attributes from

CTAS

Use Clock and Transfer

Attributes from

000

DSPI_CTAR0

100

DSPI_CTAR4

001

DSPI_CTAR1

101

DSPI_CTAR5

010

DSPI_CTAR2

110

DSPI_CTAR6

011

DSPI_CTAR3

111

DSPI_CTAR7

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