MAC7200 datasheet(674/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

596

Freescale Semiconductor

30.11.2.6 DSPI PUSH TX FIFO Register (DSPI_PUSHR)

The DSPI_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred

to the TX FIFO. See Section 30.12.3.4, “Transmit First In First Out (TX FIFO) Buffering Mechanism,”

for more information. Eight or sixteen bit write accesses to the DSPI_PUSHR will transfer 32 bits to the

TX FIFO.

RFOF_RE

Receive FIFO Overflow Request Enable. The RFOF_RE bit enables the RFOF flag in the DSPI_SR to

generate an interrupt requests.

0 RFOF interrupt requests are disabled

1 RFOF interrupt requests are enabled

Reserved, should be cleared.

RFDF_RE

Receive FIFO Drain Request Enable. The RFDF_RE bit enables the RFDF flag in the DSPI_SR to

generate a request. The RFDF_DIRS bit selects between generating an interrupt request or a DMA

request.

0 RFDF interrupt requests or DMA requests are disabled

1 RFDF interrupt requests or DMA requests are enabled

RFDF_DIRS

Receive FIFO Drain DMA or Interrupt Request Select. The RFDF_DIRS bit selects between generating

a DMA request or an interrupt request. When the RFDF flag bit in the DSPI_SR is set, and the RFDF_RE

bit in the DSPI_RSER register is set, the RFDF_DIRS bit selects between generating an interrupt request

or a DMA request.

0 Interrupt request will be generated

1 DMA request will be generated

Address: DSPI_BASE + 0x34

Access:

CONT

CTAS

EOQ CTCNT

PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0

Reset

000

TXDATA

Reset

000

Figure 30-8. DSPI PUSH TX FIFO Register (DSPI_PUSHR)

Table 30-18. DSPI_RSER Field Descriptions (Continued)

Field

Description

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