MAC7200 datasheet(678/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

600

Freescale Semiconductor

The 16-bit shift register in the Master and the 16-bit shift register in the Slave are linked by the SOUT and

SIN signals to form a distributed 32-bit register. The Master and Slave use 16-bit shift registers. When a

data transfer operation is performed, data is serially shifted a pre-determined number of bit positions.

Because the registers are linked, data is exchanged between the Master and the Slave; the data that was in

the Master’s shift register is now in the shift register of the Slave, and vice versa. At the end of a transfer,

the TCF bit in the DSPI_SR is set to indicate a completed transfer. Figure 30-12 illustrates how Master

and Slave data is exchanged.

Figure 30-12. SPI Serial Protocol Overview

The DSPI has eight Peripheral Chip Select (PCS) signals that are used to select which of the Slaves to

communicate with.

The three DSPI configurations share transfer protocol and timing properties so they are described

independently of the configuration in Section 30.12.5, “Transfer Formats”. The transfer rate and delay

settings are described in Section 30.12.4, “DSPI Baud Rate and Clock Delay Generation.”

See Section 30.12.8, “Power Saving Features,” for information on the power-saving features of the DSPI.

30.12.1 Modes of Operation

The DSPI has five distinct modes:

•

Master Mode

•

Slave Mode

•

Module Disable Mode

•

External Stop Mode

•

Debug Mode

Master, Slave, and Module Disable Modes are block-specific mode while External Stop and Debug Modes

are MCU-specific modes.

The block-specific modes are determined by bits in the DSPI_MCR. External Stop Mode and Debug Mode

are modes that the entire MCU can enter in parallel with the DSPI being configured in one of its

block-specific modes.

Shift Register

Baud Rate

Generator

Shift Register

SIN

SOUT

SCK

PCSx

DSPI Master

DSPI Slave

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