MAC7200 datasheet(681/976 Pages) FREESCALE

681 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

603

(RX FIFO) buffer. Host software or a DMA Controller transfer the received data from the RX FIFO to

memory external to the DSPI. The FIFO buffer operations are described in Section 30.12.3.4, “Transmit

First In First Out (TX FIFO) Buffering Mechanism,” and Section 30.12.3.5, “Receive First In First Out

(RX FIFO) Buffering Mechanism.” The interrupt and DMA request conditions are described in

Section 30.12.7, “Interrupts/DMA Requests.”

The SPI Configuration supports two block-specific modes; Master Mode and Slave Mode. The FIFO

operations are similar for the Master Mode and Slave Mode. The main difference is that in Master Mode

the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO

entry. In Slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI

and the SPI command field of the TX FIFO entry is ignored.

30.12.3.1 Master Mode

In SPI Master Mode the DSPI initiates the serial transfers by controlling the Serial Communications Clock

(SCK) and the Peripheral Chip Select (PCS) signals. The SPI command field in the executing TX FIFO

entry determines which CTAR registers will be used to set the transfer attributes and which PCS signal to

assert. The command field also contains various bits that help with queue management and transfer

protocol. See Section 30.11.2.6, “DSPI PUSH TX FIFO Register (DSPI_PUSHR)” for details on the SPI

command fields. The data field in the executing TX FIFO entry is loaded into the shift register and shifted

out on the Serial Out (SOUT) pin. In SPI Master Mode, each SPI frame to be transmitted has a command

associated with it allowing for transfer attribute control on a frame by frame basis.

30.12.3.2 Slave Mode

In SPI Slave Mode the DSPI responds to transfers initiated by a SPI bus master. The DSPI does not initiate

transfers. Certain transfer attributes such as clock polarity, clock phase and frame size must be set for

successful communication with a SPI master. The SPI Slave Mode transfer attributes are set in the

DSPI_CTAR0.

30.12.3.3 FIFO Disable Operation

The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI

operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are

disabled separately. The TX FIFO is disabled by writing a ‘1’ to the DIS_TXF bit in the DSPI_MCR. The

RX FIFO is disabled by writing a ‘1’ to the DIS_RXF bit in the DSPI_MCR.

The FIFO Disable mechanisms are transparent to the user and to host software; Transmit data and

commands are written to the DSPI_PUSHR and received data is read from the DSPI_POPR.When the TX

FIFO is disabled the TFFF, TFUF and TXCTR fields in DSPI_SR behave as if there is a one-entry FIFO

but the contents of the DSPI_TXFR registers and TXNXTPTR are undefined. When the RX FIFO is

disabled the RFDF, RFOF and RXCTR fields in the DSPI_SR behave as if there is a one-entry FIFO but

the contents of the DSPI_RXFR registers and POPNXTPTR are undefined.

MAC7200 Datasheet(PDF) 681 Page - Freescale Semiconductor, Inc