MAC7200 datasheet(680/976 Pages) FREESCALE

680 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

602

Freescale Semiconductor

30.12.2 Start and Stop of DSPI Transfers

The DSPI has two operating states; STOPPED and RUNNING. The states are independent of DSPI

configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are

initiated in Master Mode and no transfers are responded to in Slave Mode. The STOPPED state is also a

safe state for writing the various configuration registers of the DSPI without causing undetermined results.

The TXRXS bit in the DSPI_SR is negated in this state. In the RUNNING state serial transfers take place.

The TXRXS bit in the DSPI_SR is asserted in the RUNNING state. Figure 30-13 shows a state diagram

of the start and stop mechanism. The transitions are described in Table 30-23.

Figure 30-13. DSPI Start and Stop State Diagram

State transitions from RUNNING to STOPPED occur on the next frame boundary if a transfer is in

progress, or on the next system clock cycle if no transfers are in progress.

30.12.3 Serial Peripheral Interface (SPI) Configuration

The SPI Configuration transfers data serially using a shift register and a selection of programmable

transfer attributes. The DSPI is in SPI Configuration when the DCONF field in the DSPI_MCR is 0b00.

The SPI frames can be from four to sixteen bits long. The data to be transmitted can come from queues

stored in RAM external to the DSPI. Host software or a DMA Controller can transfer the SPI data from

the queues to a First-In First-Out (FIFO) buffer. The received data is stored in entries in the Receive FIFO

Table 30-23. State Transitions for Start and Stop of DSPI Transfers

Transition #

Current State

Next State

Description

RESET

STOPPED

Generic power-on-reset transition

STOPPED

RUNNING

The DSPI is started (DSPI transitions to RUNNING) when all of the

following conditions are true:

• EOQF bit is clear

• Debug mode is unselected or the FRZ bit is clear

• HALT bit is clear

RUNNING

STOPPED

The DSPI stops (transitions from RUNNING to STOPPED) after the

current frame for any one of the following conditions:

• EOQF bit is set

• Debug mode is selected and the FRZ bit is set

• HALT bit is set

RESET

STOPPED

RUNNING

Power on

TXRXS=0

TXRXS=1

reset

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