MAC7200 datasheet(683/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

605

DSPI_POPR or by flushing the RX FIFO.

The RX FIFO Counter field (RXCTR) in the DSPI Status Register (DSPI_SR) indicates the number of

valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is

copied from the shift register to the RX FIFO.

The POPNXTPTR field in the DSPI_SR points to the RX FIFO entry that is returned when the

DSPI_POPR is read. The POPNXTPTR contains the positive offset from DSPI_RXFR0 in number of

32-bit registers. For example, POPNXTPTR equal to two means that the DSPI_RXFR2 contains the

received SPI data that will be returned when DSPI_POPR is read. The POPNXTPTR field is incremented

every time the DSPI_POPR is read.

30.12.3.5.1

Filling the RX FIFO

The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,

SPI frames from the shift register are transferred to the RX FIFO. Every time a SPI frame is transferred to

the RX FIFO the RX FIFO Counter is incremented by one.

If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI_SR is asserted

indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI_MCR, the data from

the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit

is asserted, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the incoming

data is ignored.

30.12.3.5.2

Draining the RX FIFO

Host software or other intelligent blocks can remove (pop) entries from the RX FIFO by reading the DSPI

POP RX FIFO Register (DSPI_POPR). A read of the DSPI_POPR decrements the RX FIFO Counter by

one. Attempts to pop data from an empty RX FIFO are ignored, the RX FIFO Counter remains unchanged.

The data returned from reading an empty RX FIFO is undetermined.

When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the DSPI_SR is set. The RFDF bit

is cleared when the RX_FIFO is empty and the DMA controller indicates that a read from DSPI_POPR is

complete or by host software writing a ‘1’ to the RFDF.

30.12.4 DSPI Baud Rate and Clock Delay Generation

The SCK frequency and the delay values for serial transfer are generated by dividing the system clock

frequency by a prescaler and a scaler with the option for doubling the baud rate. Figure 30-14 shows

conceptually how the SCK signal is generated.

Figure 30-14. Communications Clock Prescalers and Scalers

SCK

System Clock

Prescaler

Scaler

1+DBR

MAC7200 Datasheet(PDF) 683 Page - Freescale Semiconductor, Inc

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