MAC7200 datasheet(673/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

595

Address: DSPI_BASE + 0x30

Access:

Reset

Figure 30-7. DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)

Table 30-18. DSPI_RSER Field Descriptions

Field

Description

TCF_RE

Transmission Complete Request Enable. The TCF_RE bit enables TCF flag in the DSPI_SR to generate

an interrupt request.

0 TCF interrupt requests are disabled

1 TCF interrupt requests are enabled

30–29

Reserved, should be cleared.

EOQF_RE

DSPI Finished Request Enable. The EOQF_RE bit enables the EOQF flag in the DSPI_SR to generate

an interrupt request.

0 EOQF interrupt requests are disabled

1 EOQF interrupt requests are enabled

TFUF_RE

Transmit FIFO Underflow Request Enable. The TFUF_RE bit enables the TFUF flag in the DSPI_SR to

generate an interrupt request.

0 TFUF interrupt requests are disabled

1 TFUF interrupt requests are enabled

Reserved, should be cleared.

TFFF_RE

Transmit FIFO Fill Request Enable. The TFFF_RE bit enables the TFFF flag in the DSPI_SR to generate

a request. The TFFF_DIRS bit selects between generating an interrupt request or a DMA requests.

0 TFFF interrupt requests or DMA requests are disabled

1 TFFF interrupt requests or DMA requests are enabled

TFFF_DIRS

Transmit FIFO Fill DMA or Interrupt Request Select. The TFFF_DIRS bit selects between generating a

DMA request or an interrupt request. When the TFFF flag bit in the DSPI_SR is set, and the TFFF_RE

bit in the DSPI_RSER register is set, this bit selects between generating an interrupt request or a DMA

request.

0 Interrupt request will be generated

1 DMA request will be generated

23–20

Reserved, should be cleared.

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