MAC7200 datasheet(672/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

594

Freescale Semiconductor

30.11.2.5 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)

The DSPI_RSER serves two purposes. It enables flag bits in the DSPI_SR to generate DMA requests or

interrupt requests. The DSPI_RSER also selects the type of request to be generated. See the individual bit

descriptions for information on the types of requests the bits support. The user must not write to the

DSPI_RSER while the DSPI is in the Running state.

RFOF

Receive FIFO Overflow Flag. The RFOF bit indicates that an overflow condition in the RX FIFO has

occurred. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit

remains set until cleared by software.

0 RX FIFO overflow has not occurred

1 RX FIFO overflow has occurred

Reserved, should be cleared.

RFDF

Receive FIFO Drain Flag. The RFDF bit provides a method for the DSPI to request that entries be

removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared

by host software or an acknowledgement from the DMA controller when the RX FIFO is empty.

0 RX FIFO is empty

1 RX FIFO is not empty

Reserved, should be cleared.

15–12

TXCTR

TX FIFO Counter. The TXCTR field indicates the number of valid entries in the TX FIFO. The TXCTR is

incremented every time the DSPI _PUSHR is written. The TXCTR is decremented every time a SPI

command is executed and the SPI data is transferred to the shift register.

11–8

TXNXTPTR

Transmit Next Pointer. The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the

next transfer. The TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the

shift register. See Section 30.12.7.4, “Transmit FIFO Underflow Interrupt Request,” for more details.

7–4

RXCTR

RX FIFO Counter. The RXCTR field indicates the number of entries in the RX FIFO. The RXCTR is

decremented every time the DSPI _POPR is read. The RXCTR is incremented every time data is

transferred from the shift register to the RX FIFO.

3–0

POPNXTPTR

Pop Next Pointer. The POPNXTPTR field contains a pointer to the RX FIFO entry that will be returned

when the DSPI_POPR is read. The POPNXTPTR is updated when the DSPI_POPR is read. See

Section 30.12.3.5, “Receive First In First Out (RX FIFO) Buffering Mechanism,” for more details.

Table 30-17. DSPI_SR Field Descriptions (Continued)

Field

Description

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