MAC7200 datasheet(668/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

590

Freescale Semiconductor

11–8

ASC[3:0]

After SCK Delay Scaler. The ASC field selects the scaler value for the After SCK Delay. This field is only

used in Master Mode. The After SCK Delay is the delay between the last edge of SCK and the negation

of PCS. Table 30-14 list the scaler values.The After SCK Delay is a multiple of the system clock period,

and it is computed according to the following equation:

Eqn. 30-3

See Section 30.12.4.3, “After SCK Delay (tASC),” for more details.

7–4

DT[3:0]

Delay after Transfer Scaler. The DT field selects the Delay after Transfer Scaler. This field is only used in

Master Mode. The Delay after Transfer is the time between the negation of the PCS signal at the end of

a frame and the assertion of PCS at the beginning of the next frame. Table 30-15 lists the scaler values..

In the Continuous Serial Communications Clock operation the DT value is fixed to one TSCK. The Delay

after Transfer is a multiple of the system clock period and it is computed according to the following

equation:

Eqn. 30-4

See Section 30.12.4.4, “Delay after Transfer (tDT),” for more details.

3–0

BR[3:0]

Baud Rate Scaler. The BR field selects the scaler value for the baud rate. This field is only used in Master

Mode. The pre-scaled system clock is divided by the Baud Rate Scaler to generate the frequency of the

SCK. Table 30-16 lists the Baud Rate Scaler values.The baud rate is computed according to the following

equation:

Eqn. 30-5

See Section 30.12.4.1, “Baud Rate Generator,” for more details.

Table 30-11. DSPI SCK Duty Cycle

DBR

CPHA

PBR

SCK Duty Cycle

any

50/50

33/66

40/60

43/57

50/50

66/33

60/40

57/43

Table 30-10. DSPI_CTARn Field Descriptions (Continued)

Field

Descriptions

ASC

SYS

-----------

PASC

ASC

SYS

-----------

PDT

SCK baud rate

SYS

PBR

-------------

1DBR

-----------------------

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