MAC7200 datasheet(664/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

586

Freescale Semiconductor

30.11.2.2 DSPI Transfer Count Register (DSPI_TCR)

The DSPI_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter

is intended to assist in queue management. The user must not write to the DSPI_TCR while the DSPI is in

the Running state.

CLR_RXF

Clear RX FIFO. CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the RX Counter.

The CLR_RXF bit is always read as zero.

0 Do not clear the RX FIFO Counter

1 Clear the RX FIFO Counter

9–8

SMPL_PT

SMPL_PT — Sample Point. SMPL_PT allows the host software to select when the DSPI Master samples

SIN in Modified Transfer Format. Figure 30-18 shows where the Master can sample the SIN pin. The table

below lists the various delayed sample points.

7–1

Reserved, should be cleared.

HALT

Halt. The HALT bit provides a mechanism by software to start and stop DSPI transfers. See

Section 30.12.2, “Start and Stop of DSPI Transfers,” for details on the operation of this bit.

0 Start transfers

1 Stop transfers

Address: DSPI_BASE + 0x8

Access:

SPI_TCNT

Reset

000000000000000

9876543210

000000000000000

Reset

000000000000000

Figure 30-4. DSPI Transfer Count Register (DSPI_TCR)

Table 30-8. DSPI_MCR Field Descriptions (Continued)

Field

Description

SMPL_PT

Number of system clock cycles between odd-numbered edge of

SCK and sampling of SIN.

Reserved

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