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MAC7200 Datasheet(PDF) 667 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 667 Page - Freescale Semiconductor, Inc

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Memory Map and Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
589
21–20
PASC[1:0]
After SCK Delay Prescaler. The PASC field selects the prescaler value for the delay between the last edge
of SCK and the negation of PCS. This field is only used in Master Mode. The table below lists the
prescaler values. See the ASC[3:0] field description for details on how to compute the After SCK Delay.
19–18
PDT[1:0]
Delay after Transfer Prescaler. The PDT field selects the prescaler value for the delay between the
negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next
frame. The PDT field is only used in Master Mode. The table below lists the prescaler values. See the
DT[3:0] field description for details on how to compute the Delay after Transfer.
17–16
PBR[1:0]
Baud Rate Prescal. The PBR field selects the prescaler value for the baud rate. This field is only used in
Master Mode. The Baud Rate is the frequency of the Serial Communications Clock (SCK). The system
clock is divided by the prescaler value before the baud rate selection takes place. The Baud Rate
Prescaler values are listed in the table below. See the BR[3:0] field description for details on how to
compute the baud rate.
15–12
CSSCK[3:0]
PCS to SCK Delay Scaler. The CSSCK field selects the scaler value for the PCS to SCK delay. This field
is only used in Master Mode. The PCS to SCK Delay is the delay between the assertion of PCS and the
first edge of the SCK. Table 30-13 list the scaler values.The PCS to SCK Delay is a multiple of the system
clock period and it is computed according to the following equation:
Eqn. 30-2
See Section 30.12.4.2, “PCS to SCK Delay (tCSC),” for more details.
Table 30-10. DSPI_CTARn Field Descriptions (Continued)
Field
Descriptions
PASC
After SCK Delay Prescaler Value
00
1
01
3
10
5
11
7
PDT
Delay after Transfer Prescaler Value
00
1
01
3
10
5
11
7
PBR
Baud Rate Prescaler Value
00
2
01
3
10
5
11
7
t
CSC
1
f
SYS
-----------
PCSSCK
CSSCK
×
×
=



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