MAC7200 datasheet(663/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

585

FRZ

Freeze. The FRZ bit enables the DSPI transfers to be stopped on the next frame boundary when the SoC

enters Debug Mode.

0 Do not halt serial transfers1Halt serial transfers

MTFE

Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used. See

Section 30.12.5.4, “Modified SPI Transfer Format (MTFE = 1, CPHA = 1),” for more information.

0 Modified SPI transfer format disabled

1 Modified SPI transfer format enabled

PCSSE

Peripheral Chip Select Strobe Enable. The PCSSE bit enables the PCS[5]/PCSS to operate as an PCS

Strobe output signal. See Section 30.12.4.5, “Peripheral Chip Select Strobe Enable (PCSS),” for more

information.

0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal

1 PCS[5]/PCSS is used as an active-low PCS Strobe signal

ROOE

Receive FIFO Overflow Overwrite Enable. The ROOE bit enables an RX FIFO overflow condition to either

ignore the incoming serial data or to overwrite existing data. If the RX FIFO is full and new data is

received, the data from the transfer that generated the overflow is either ignored or shifted in to the shift

is negated, the incoming data is ignored. See Section 30.12.7.6, “Receive FIFO Overflow Interrupt

Request,” for more information.

0 Incoming data is ignored

1 Incoming data is shifted in to the shift register

23–16

PCSISx

Peripheral Chip Select Inactive State. The PCSIS bit determines the inactive state of the PCSx signal.

0 The inactive state of PCSx is low

1 The inactive state of PCSx is high

DOZE

Doze Enable. The DOZE bit provides support for externally controlled Doze Mode power-saving

mechanism. See Section 30.12.8, “Power Saving Features,” for details.

MDIS

Module Disable. The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the

DSPI effectively putting the DSPI in a software controlled power-saving state. See Section 30.12.8,

“Power Saving Features,” for more information. The reset value of the MDIS bit is parameterized, with a

default reset value of ‘0’.

0 Enable DSPI clocks.

1 Allow external logic to disable DSPI clocks.

DIS_TXF

Disable Transmit FIFO. The DIS_TXF bit provides a mechanism to disable the TX FIFO. When the TX

FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. See

Section 30.12.3.3, “FIFO Disable Operation,” for details.

0 TX FIFO is enabled

1 TX FIFO is disabled

DIS_RXF

Disable Receive FIFO. The DIS_RXF bit provides a mechanism to disable the RX FIFO. When the RX

FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. See

Section 30.12.3.3, “FIFO Disable Operation,” for details.

0 RX FIFO is enabled

1 RX FIFO is disabled

CLR_TXF

Clear TX FIFO. CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX FIFO

Counter. The CLR_TXF bit is always read as zero.

0 Do not clear the TX FIFO Counter

1 Clear the TX FIFO Counter

Table 30-8. DSPI_MCR Field Descriptions (Continued)

Field

Description

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