MAC7200 datasheet(661/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

583

30.10.2.5 PCS[6] - PCS[7] — Peripheral Chip Selects 6- 7

PCS[6] - PCS[7] are Peripheral Chip Select output signals in Master Mode. In Slave Mode these signals

are not used.

30.10.2.6 SIN — Serial Input

SIN is a serial data input signal.

30.10.2.7 SOUT — Serial Output

SOUT is a serial data output signal.

30.10.2.8 SCK — Serial Clock

SCK is a serial communication clock signal. In Master Mode, the DSPI generates the SCK. In Slave Mode,

SCK is an input from an external bus master.

30.11 Memory Map and Register Definition

30.11.1 Memory Map

Table 30-7 shows the DSPI memory map.

Table 30-7. DSPI Memory Map

Address

DSPI_BASE

DSPI Module Configuration Register (DSPI_MCR)

DSPI_BASE+0x4

Reserved

DSPI_BASE+0x8

DSPI Transfer Count Register (DSPI_TCR)

DSPI_BASE+0xC–

DSPI_BASE+0x28

DSPI Clock and Transfer Attributes Register 0 (DSPI_CTAR0) -

DSPI Clock and Transfer Attributes Register 7 (DSPI_CTAR7)1

1. The number of CTAR registers is parameterized in RTL.

DSPI_BASE+0x2C

DSPI Status Register (DSPI_SR)

DSPI_BASE+0x30

DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)

FIFO Registers

DSPI_BASE+0x34

DSPI Push TX FIFO Register (DSPI_PUSHR)

DSPI_BASE+0x38

DSPI Pop RX FIFO Register (DSPI_POPR)

DSPI_BASE+0x3C -

DSPI_BASE+0x48

DSPI Transmit FIFO Register 0 (DSPI_TXFR0) -

DSPI Transmit FIFO Register 3 (DSPI_TXFR3)2

2. FIFO Depths are parameterized in RTL.

DSPI_BASE+0x4C -

DSPI_BASE+0x58

DSPI Receive FIFO Register 0 (DSPI_RXFR0) -

DSPI Receive FIFO Register 3 (DSPI_RXFR3)2

MAC7200 Datasheet(PDF) 661 Page - Freescale Semiconductor, Inc

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