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MAC7200 Datasheet(PDF) 662 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 662 Page - Freescale Semiconductor, Inc

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Memory Map and Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
584
Freescale Semiconductor
30.11.2 Register Descriptions
30.11.2.1 DSPI Module Configuration Register (DSPI_MCR)
The DSPI_MCR contains bits which configure various attributes associated with DSPI operation. The
HALT and MDIS bits can be changed at any time but will only take effect on the next frame boundary.
Only the HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is in the Running state.
Address: DSPI_BASE
Access:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
MSTR
DCONF
FRZ
MTFE
ROOE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
DOZE
MDIS
SMPL_PT
0
0
00
00
0
HALT
W
Reset
0
01
0
0
0
0
0
0
0
0
00
00
0
1
1 MDIS reset value is paramaterized in RTL.
Figure 30-3. DSPI Module Configuration Register (DSPI_MCR)
Table 30-8. DSPI_MCR Field Descriptions
Field
Description
31
MSTR
Master/Slave Mode Select. The MSTR bit configures the DSPI for either Master Mode or Slave Mode.
0 DSPI is in Slave Mode
1 DSPI is in Master Mode
30
CONT_SCKE
Continuous SCK Enable. The CONT_SCKE bit enables the Serial Communication Clock (SCK) to run
continuously. See Section 30.12.6, “Continuous Serial Communications Clock,” for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
29–28
DCONF[1:0]
DSPI Configuration. The DCONF field selects the configuration of the DSPI. As only the SPI configuration
is implemented on the MAC72xx, the DCONF bits must always be set to 00..
DCONF
DSPI Configuration
00
SPI
01
Reserved
10
Reserved
11
Reserved



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