MAC7200 datasheet(666/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

588

Freescale Semiconductor

Table 30-10. DSPI_CTARn Field Descriptions

Field

Descriptions

DBR

Double Baud Rate. The DBR bit doubles the effective baud rate of the Serial Communications Clock

(SCK). This field is only used in Master Mode. It effectively halves the Baud Rate division ratio supporting

faster frequencies and odd division ratios for the Serial Communications Clock (SCK). When the DBR bit

is set, the duty cycle of the Serial Communications Clock (SCK) depends on the value in the Baud Rate

Prescaler and the Clock Phase bit as listed in Table 30-11. See the BR[3:0] field description for details on

how to compute the baud rate. If the overall baud rate is divide by two or divide by three of the system

clock then neither the Continuous SCK Enable or the Modified Timing Format Enable bits should be set.

0 The baud rate is computed normally with a 50/50 duty cycle

1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler

30–27

FMSZ[3:0]

Frame Size. The FMSZ field selects the number of bits transferred per frame. The FMSZ field is used in

Master Mode and Slave Mode. Table 30-12 lists the frame sizes..

CPOL

Clock Polarity. The CPOL bit selects the inactive state of the Serial Communications Clock (SCK). This

bit is used in both Master and Slave Mode. For successful communication between serial devices, the

devices must have identical clock polarities. When the Continuous Selection Format is selected, switching

between clock polarities without stopping the DSPI can cause errors in the transfer due to the peripheral

device interpreting the switch of clock polarity as a valid clock edge.

0 The inactive state value of SCK is low

1 The inactive state value of SCK is high

CPHA

Clock Phase. The CPHA bit selects which edge of SCK causes data to change and which edge causes

data to be captured. This bit is used in both Master and Slave Mode. For successful communication

between serial devices, the devices must have identical clock phase settings.

0 Data is captured on the leading edge of SCK and changed on the following edge

1 Data is changed on the leading edge of SCK and captured on the following edge

LSBFE

LSB First. The LSBFE bit selects if the LSB or MSB of the frame is transferred first. This bit is only used

in Master Mode.

0 Data is transferred MSB first

1 Data is transferred LSB first

23–22

PCSSCK[1:0]

PCS to SCK Delay Prescaler. The PCSSCK field selects the prescaler value for the delay between

assertion of PCS and the first edge of the SCK. This field is only used in Master Mode. The table below

lists the prescaler values. See the CSSCK[3:0] field description for details on how to compute the PCS to

SCK Delay.

PCSSCK

PCS to SCK Delay Prescaler Value

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