MAC7200 datasheet(665/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

587

30.11.2.3 DSPI Clock and Transfer Attributes Registers 0–7

(DSPI_CTAR0–DSPI_CTAR7)

The DSPI_CTAR registers are used to define different transfer attribute configurations. SPI transfers select

which one of the DSPI_CTARs to get their transfer attributes from. The number of CTAR registers is

parameterized in the RTL and can be from two to eight registers. The user must not write to the

DSPI_CTAR registers while the DSPI is in the Running state.

In Master Mode, the DSPI_CTAR0 - DSPI_CTAR7 registers define combinations of transfer attributes

such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In Slave

Mode, a subset of the bitfields in the DSPI_CTAR0 and DSPI_CTAR1 registers are used to set the slave

transfer attributes. See the individual bit descriptions for details on which bits are used in Slave Modes.

When the DSPI is configured as an SPI Master, the CTAS field in the command portion of the TX FIFO

entry selects which of the DSPI_CTAR register is used. When the DSPI is configured as an SPI bus Slave,

the DSPI_CTAR0 register is used.

Table 30-9. DSPI_TCR Field Descriptions

Field

Description

31–16

SPI_TCNT[15

:0]

SPI Transfer Counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The

SPI_TCNT field counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented

every time the last bit of a SPI frame is transmitted. A value written to SPI_TCNT presets the counter to

that value. SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the

executing SPI command. The Transfer Counter ‘wraps around’ i.e. incrementing the counter past 65535

resets the counter to zero.

15–0

Reserved, should be cleared.

Address: DSPI_BASE + 0xC–DSPI_BASE + 0x28

Access:

DBR

FMSZ

CPOL CPHA

LSBFE

PCSSCK

PASC

PDT

PBR

Reset

0000

3210

CSSCK

ASC

Reset

0000

Figure 30-5. DSPI Clock and Transfer Attributes Register 0–7 (DSPI_CTAR0–DSPI_CTAR7)

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