MAC7200 datasheet(658/976 Pages) FREESCALE

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DSPI Module

MAC7200 Microcontroller Family Reference Manual, Rev. 2

580

Freescale Semiconductor

30.9.2

Overview

The Deserial Serial Peripheral Interface (DSPI) block provides a synchronous serial bus for

communication between an MCU and an external peripheral device. The DSPI supports pin count

reduction through serialization and deserialization of parallel signals transmitted over the SPI serial link.

The DSPIs implemented on MAC72xx have one configuration:

•

Serial Peripheral interface (SPI) Configuration where the DSPI operates as a basic SPI or as a

queued SPI through the use of internal FIFOs.

For queued operations the SPI queues reside in system RAM which is external to the DSPI. Data transfers

between the queues and the DSPI FIFOs are accomplished through the use of a DMA controller or through

host software. Figure 30-2 shows a DSPI with external queues in system RAM.

Figure 30-2. DSPI with Queues and DMA

30.9.3

DSPI Configuration

The DSPI block used on MAC72xx has one distinct serial transmission configuration: SPI.

30.9.3.1

SPI Configuration

The SPI Configuration allows the DSPI to send and receive serial data. This configuration allows the DSPI

to operate as a basic SPI block with the FIFOs providing support for external queue operation. Data to be

transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed by host

software or by a DMA controller.

30.9.4

Modes of Operation

The DSPI has five modes of operation that can be grouped into two categories: block-specific modes, i.e.,

Master, Slave, and Module Disable Modes; and MCU-specific modes, i.e., External Stop and Debug

Modes.

System RAM

DSPI

DMA Controller

TX Queue

RX FIFO

TX FIFO

Shift Register

Data

Addr/Ctrl

RX Queue

Data

Addr/Ctrl

MAC7200 Datasheet(PDF) 658 Page - Freescale Semiconductor, Inc

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