MAC7200 datasheet(654/976 Pages) FREESCALE

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DSPI Implementation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

576

Freescale Semiconductor

•

MISO (Master Input/Slave Output): Data is received into this pin if the chip is a Master and

transmitted out of this pin if the chip is a Slave. This signal is bussed (i.e., 1 signal for all Slaves).

•

CS (Chip Select - active low): Point to point connection between a Master and a Slave that is used

to select a Slave for a particular transfer. On the slave side, it is sometimes referred to as a Slave

Select.

A typical SPI bus consists of a single Master and one or more slaves. Selection between Master and Slave

may be dynamic (i.e., software selectable), resulting in a (possibly) dynamic network topography. The

Master on the bus is always responsible for driving the clock (SCK), with the possibility of inserting wait

states by holding the clock low. Data transfers over a SPI bus are always done in 8-bit chunks (bytes), with

a single transfer consisting of 1 or more bytes. Data on the MOSI and MISO lines is always driven and

sampled with respect to SCK, with one of a defined set of 4 clock phase and polarities.

One of these combinations is selected (either as a static configuration or on a transfer by transfer basis)

using the two control bits CPOL and CPHA. These combinations are shown in Table 30-1.

The SPI protocol itself does not specify the content of the data, only the physical transmission of the bits.

Thus, there are no defined addressing or data packet schemes, leaving the software to implement the upper

layers of the SPI protocol stack.

30.4

DSPI Implementation

The DSPI module has several different configuration options. On the MAC72xx device, the DSPI modules

have the following configuration:

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MDIS Reset Value: The reset value of the MDIS bit is 1, meaning that the DSPI is in a disabled

state after reset, and must be explicitly enabled before it can be used.

•

Number of CTAR Registers: The number of Clock and Transfer Attributes Registers (CTAR) on

the MAC72xx is configured to 6 per DSPI.

•

Transmit FIFO Size: The size of the transmit FIFOs on all DSPIs on the MAC72xx is set to a depth

of 4 per DSPI.

•

Receive FIFO Size: The size of the receive FIFOs on all DSPIs on the MAC72xx is set to a depth

of 4 per DSPI.

Table 30-1. CPOL and CPHA Control Bits

CPOL

CPHA

Transfer Characteristics

SCK rising edge is used.

SCK transitions in the middle of the bit timing.

SCK rising edge is used.

SCK transitions at the beginning of the bit timing.

SCK falling edge is used.

SCK transitions in the middle of the bit timing.

SCK falling edge is used.

SCK transitions at the beginning of the bit timing.

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