MAC7200 datasheet(651/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

573

bringing the system back into a ’ready-for-I2C-transfer’ state. The advantage over the two other

solutions is that this neigher requires CPU intervention nor a 2nd DMA channel. This comes at the

cost of 64 bytes RAM (2 TCDs), some system bus transfer overhead and a little increase in

application code complexity. Please note that you have to make sure on system level that no higher

priority DMA requests occur during the scatter/gather process, as those could again create a

scenario of slow reaction.

Example latencies for a 32 MHz system with a full speed 32bit AHB bus and an I2C connected via half

speed IPI bus:

•

Accessing the I2C from the DMA controller via IPI bus typically requires 4 cycles (consecutive

accesses to the I2C could be faster):

4 x TIPI = 4 / 16 MHz = 250 ns

Eqn. 29-6

•

Reloading a new TCD (8 x 32 bit) via AHB to the DMA controller (scatter/gather process):

8 x TAHB = 8 / 32 MHz = 250 ns

Eqn. 29-7

Conclusion:

With the DMA scatter/gather process the required IBCR access can be done in 0.5 us, leaving a large

margin of 19.5 us for additional system delays. In this way the slow reaction case can be prevented. The

system user needs to decide which usage model suits his overall requirements best.

MAC7200 Datasheet(PDF) 651 Page - Freescale Semiconductor, Inc